This invention relates generally to non-volatile memory cells and, more particularly, to a non-volatile memory cell for a linear metal oxide semiconductor (MOS) integrated circuit.
Precision performance by a linear MOS integrated circuit is typically accomplished by internally trimming the circuit currents and voltages. Conventional trimming techniques are performed as part of the manufacturing process and must be permanent so that the trimming does not change when power is removed from the circuit. Several techniques use a fuse-based technology, such as the metal spike shorting of the emitter-base junction of a NPN transistor, or the opening of metal or thin film links, that require high current pulses to sever the subject material. Another method requires specialized equipment for the laser trimming of thin film links or the vernier trim of thin film resistor tabs, which may drift over time. All of these techniques are intended for low-density memory applications. High-density storage techniques use either "anti-fuse" technology or place a long-term charge storage on the MOSFET gates. These techniques, however, add complex processing steps to wafer fabrication and extra cost to the device.
What is needed, therefore, is an inexpensive and user-programmable technique for performing a parametric trim of a linear MOS integrated circuit.